蔡仁松 教授 1980年畢業於台灣大學電機工程系。1985年申請進入柏克萊大學，並取得電機工程及電腦博士學位。畢業後至 IBM 公司研發部工作。1992年參與起創 ArcSys 公司( 後合併入 Synopsys )，並任產品設計總監，發展世界第一個成功的 IC 速率優化設計工具。1997年另再創辦 Axis 公司( 現併入 Cadence )，設計製作一個可以用軟體隨意組架的電腦系統( Reconfigurable Computer )，市場上銷售非常成功。蔡教授的長處在於結合理論與實務，而開發多項業界必用的產品。由於經驗豐富，國內外多家公司邀聘為顧問及董事。2004及2005暑期應清華大學電資學院邀請任特聘講座。現為清華大學專任教授。除專業課程外，亦教授「高科技創業學」傳遞創業經驗。

個人擁有多項專利。在 IEEE 雜誌發表過數十篇專業論文，並榮獲該雜誌頒發之電腦輔助設計最佳論文獎。另獲選 ICCAD 20 年最佳論文。亦曾獲 IBM 公司之技術成就獎。

Dr. Ren-Song Tsay, nicknamed “Dr. Zero-Skew”, is the inventor of the famous industry standard zero-skew clock tree design method.

He received his Ph. D. degree from UC Berkeley and worked for IBM T. J.Watson Research Center before he started his successful Silicon Valley ventures. He was the person designed the first commercially successful performance optimization physical design system (now in Synopsys) which is still the market leader. He then jointly founded Axis Systems (now merged with Cadence) and developed a breakthrough logic verification system using reconfigurable computer technology. After that, he helped a few start-up companies as a consultant or investor.

Wishing to pass on his experiences to younger generation, he is now teaching at National Tsing-Hua University, Taiwan, his home country, on the subjects of “High-Tech Entrepreneurship” and “System Level Design”.

Dr. Tsay is a devout Christian and a well respected person for his integrity, insight and ingenuity.

Latest Update: 2011.4.1

• 2010-now ASPDAC Steering Committe
• 2018 SASIMI Best Paper Award
• 2016.10 SASIMI Outstanding Paper Award
• 2016.6第十屆龍騰微笑創業競賽佳作獎，” 超省電智慧感測追縱器與雲端服務”，黃超明、陳逸樺、林麗郁、陳為方、陳正林

• 2015 TITC 社會貢獻獎
• 2013 中華民國資訊學會最佳博士論文獎佳作, “利用時脈數精準的交易層級塑模進行快且準的多核心單晶片系統模擬”, 博士生羅振綱
• 2012.3 SASIMI Outstanding Paper Award
• 2011.5 國內凌陽盃系統晶片創意應用大賽優勝及佳作獎
• 2010.7 指導的Power Saviors隊伍獲茂迪盃-太陽能光電應用設計創意競賽最佳設計獎
• 2009.11 國科會晶片系統國家型計畫績優計畫獎
• 2009 ASP-DAC Best poster award
• 2003: “Exact Zero Skew” chosen in “The Best of ICCAD 20 Years” published by Kluwer Academic Publishers
• 1993-1998: serving in program committees of ICCAD, DAC, and International Symposium on Physical Design (ISPD).
• 1993: IEEE Transaction on CAD Best Paper Award
• 1991 IBM Outstanding Technical Achievement Award

1. Be honest no cheating

2. Be a team

2.1   Share ideas and information

2.2   Help each other to succeed

2.3   Be open on any Lab business

2.4   Share Lab chores

2.5   Complement, not criticize, people’s weakness

2.6   Praise and appreciate people’s achievement

3. Be respectful

3.1   When doing anything in the Lab, try not to disturb others.

3.2   Respect each other

4. Be responsible

4.1   Fulfill any commitment and job responsibility

5. Be disciplined

5.1   Try to be in the office during weekday daytime

5.2   Finish projects on time

6. Be balanced

6.1   Keep a balanced, healthy, regular life style

6.2   Keep a broad, yet healthy, interests besides technical knowledge

7. Be clean

7.1   Take turn to clean Lab and maintain it clean.

● Professor

蔡仁松

● Part-time postgraduate students

吳昕益

● Ph.D. students

 楊奕君 江政勳

● Master students

王睿哲 李柏漢 王念祖

● Alumni

2008年 林凱立 羅億綸

2009年 李建旻

2010年 莊震宇 傅正陽 王鵬智 杜浩銓

2011年 吳孟寰 利茂霖 呂沂善

2012年 黃毓閎 陳立君 林沛佳 羅振綱 曾柏翰 游凡緯 黃子齊 白憲倫

2013年 張豐願 陳書湧 陳慶諭

2014年 張鈞皓

2015年 陳建豪 李柏均 蕭啟廷 陳萱蔓

2016年 蔡政霖

2017年 林軒毅 何芯瑀

2018年 張筠 胡宇康 張瑋鑫

2019年 金國丞 郭達毅 呂宗穎 理艾辛

2020年 葉揚 黃翊紘 凌胤淳 李佳齊

2021年 金緒勳 郭韋逸

2023年 陳詠瑄 盧冠甫 高瑞宏

2024年 李冠學 蘇子軒 彭湘婷 蔡惟恩 陳唯中

• Blockchain Core Technology and Applications
  • Consensus algorithm
  • Multi-threaded chaining
  • FinTech - automatic auditing system
  • E-Voting system
• Distributed Secure IoT framework
  • Self-sovereign eId
  • An ultra-robust private key management system
  • Self-sovereign access control protocol
  • Peer-to-peer transaction model
  • Privacy-preserving techniques
• Trusted Computing and Hardware Security Chip
  • Trusted computing environment
  • Secure element
  • Hardware eWallet
• Dafuon Entrepreneurship education system
  • Gamified education system
  • Resource map and scheduling
  • Personal talent exploration and team formation
• Entrepreneurship learning map

[Recent publications]

Books:

1. 「高科技創業與營運教師手冊」蔡仁松著,2021, 清大出版
2. 「6小時從零到一: 高科技創業入門教師手冊」蔡仁松著,2021, 清大出版
3. 「創新創意與創業課程教師手冊」蔡仁松著，2021, 社團法人台灣佳美生命建造協會
4. 「 高科技創業與營運」蔡仁松著,2021. 社團法人台灣佳美生命建造協會
5. 「創新創意與創業」蔡仁松著，2021, 社團法人台灣佳美生命建造協會
6. 「6小時從零到一: 高科技創業入門」蔡仁松著,2020, 奇智出版
7. 「道在人間」蔡仁松著,2019, 台灣佳美協會出版
8. 「傾聽他的心引導員手冊」蔡仁松 李富華著，2019, 社團法人台灣佳美生命建造協會出版
9. 「天問旅程」蔡仁松著,2017, 台灣佳美協會出版
10. 「蟲蟲危機大作戰」蔡仁松 李富華著，2017, 社團法人台灣佳美生命建造協會出版
11. 「理理力溝通」蔡仁松 李富華著，2017, 社團法人台灣佳美生命建造協會出版
12. 「心靈地圖」蔡仁松 李富華著，2017, 社團法人台灣佳美生命建造協會出版

Journal Papers:

1. Hsin-I Wu, Da-Yi Guo, and Ren-Song Tsay, “A Virtualization-Assisted Full-System Simulation Approach for the Verification of System Inter-Component Interactions,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2020
2. Jyun-Hao Chang, Hsin-I Wu, Hsien-Lun Pai, Ren-Song Tsay, Wai-Kei Mak, “Highly Efficient and Effective Approach for Synchronization-Function-Level Parallel Multicore Instruction-Set Simulations.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 34.11 (2015): 1822-1835.
3. Chang, F-Y., R-S. Tsay, W-K. Mak, and S-H. Chen. “MANA: A Shortest Path Maze Algorithm Under Separation and Minimum Length NAnometer Rules.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 32, no. 10 (2013): 1557-1568.
4. Chen-Kang Lo, Mao-Lin Li, Jen-Chieh Yeh, Ren-Song Tsay, “Automatic Generation of High-speed Accurate TLM Models for Out-of-Order Pipelined Bus,” ACM Transactions on Embedded Computing Systems, 2013.
5. Meng-Huan Wu, Cheng-Yang Fu, Peng-Chih Wang, Ren-Song Tsay, “A Distributed Timing Synchronization Technique for Parallel Multi-Core Instruction-Set Simulation,” ACM Transactions on Embedded Computing Systems, Feb. 2013.
6. Meng-Huan Wu, Peng-Chih Wang, Cheng-Yang Fu, and Ren-Song Tsay, “An Extended SystemC Framework for Efficient and Reliable HW/SW Co-Simulation,” ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 17 Issue 2, April 2012
7. Ching-Te Chiu , Tsun-Hsien Wang , Wei-Ming Ke , Chen-Yu Chuang , Jhih-Siao Huang , Wei-Su Wong , Ren-Song Tsay, and Cyuan-Jhe Wu, “Real-Time Tone-Mapping Processor with Integrated Photographic and Gradient Compression using 0.13 μm Technology on an Arm Soc Platform,” Journal of Signal Processing Systems, Springer, June 2010.

International Conference Papers:

1. You-En Wu, Hsin-I Wu, Kuo-Cheng Chin, Yi-Chun Yang and Ren-Song Tsay, “Accelerate Large Language Model Inference on Edge TPU with OpenVX framework,” AICAS 2024
2. Hsuan-Yi Lin and Ren-Song Tsay, “Accurate Performance Estimation with BBFDA: Beyond Granularity Constraints,” SASIMI 2024
3. Hsuan-Yi Lin and Ren-Song Tsay, “Beyond Time-Quantum: A Basic-Block FDA Approach for Accurate System Computing Performance Estimation,” ASP-DAC 2024
4. Guan-Shiue Li and Ren-Song Tsay, “A Verifiable I/O Approach for End-to-end Eligibility Verifiability in Black-box E-Voting Systems,” the 17th International Conference on Telecommunication Systems, Services, and Applications (TSSA) 2023.
5. Kuanfu Lu, Ren-Song Tsay and Yichun Yang, “A Low-Cost and Efficient Hardware Security Solution for Safeguarding Embedded Systems,” TJCASxTKCAS 2023
6. Zheng-Xun Jiang and Ren-Song Tsay, “Double-Linked Blockchain with Proof-of-Refundable-Tax for Improved Performance and Fairness,” 2023 International Conference on Information Management (ICIM)
7. Wei-Hsin Chang and Ren-Song Tsay, “A Secure and Reliable Private Key Recovery Method,” 2023 International Conference on Consumer Electronics (ICCE)
8. Yi-Chun Yang and Ren-Song Tsay, “Ureka: A Decentralized and Secure System for Managing Personal IoT Devices,” 2023 International Conference on Consumer Electronics (ICCE)
9. Jui-Hung Kao and Ren-Song Tsay, “Preventing Financial Statement Fraud with Blockchain-based Verifiable Accounting System,“ The 3rd International Conference on Electrical, Computer, Communications and Mechatronics Engineering (ICECCME‘23)
10. Yi-Chun Yang and Ren-Song Tsay, “A Decentralized Solution for Secure and Transparent Management of IoT Access Rights,” the Second International Conference on Innovations in Computing Research (ICR‘23)
11. Hsu-Hsun Chin, Ren-Song Tsay, and Hsin-I Wu, “An Adaptive High-Performance Quantization Approach for Resource-Constrained CNN Inference,” The 4th IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS 2022)
12. Chong-Yin Lu, Ren-Song Tsay, and Weyshin Chang “An Embedded CNN Design for Edge Devices Based on Logarithmic Computing,” VLSI-DAT 2022
13. Kuo-Cheng Chin, Ren-Song Tsay, and Hsin-I Wu, “A Heuristic Region-based Concurrency Bug Testing Approach,” the 19th International Conference on Ubiquitous Computing and Communications (IUCC-2020)
14. Yin-Chun Ling, Hsu-Hsun Chin, Hsin-I Wu and Ren-Song Tsay, “Designing A Compact Convolutional Neural Network Processor on Embedded FPGAs,” 2020 IEEE GCAIoT
    Hsin-I Wu, Fong-Yuan Chang, Ren-Song Tsay,“CORONA: A k-COnnected RObust Interconnection Network Generation Algorithm,” VLSI-DAT 2020
15. Hsin-I Wu, Fong-Yuan Chang, Ren-Song Tsay, “CORONA: A k-COnnected RObust Interconnection Network Generation Algorithm,” VLSI-DAT 2020
16. Hsin-I Wu, Da-Yi Guo, Ren-Song Tsay, and Hsu-Hsun Chin, “A Pipeline-Based Scheduler for Optimizing Latency of Convolution Neural Network Inference over Heterogeneous Multicore Systems,” The 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS 2020)
17. Hsin-I Wu, Ren-Song Tsay and Hsu-Hsun Chin, “VIRA: A Virtualization Assisted Deterministic System-Level Simulations,” The 35th ACM/SIGAPP Symposium on Applied Computing (SAC 2020)
18. Asheen Lateilla Richards and Ren-Song Tsay, “An optimal slack-based course scheduling algorithm for personalised study plans,” 2020 9th International Conference on Educational and Information Technology (ICEIT 2020)
19. Chi-Kang Chen, Hsin-I Wu, Cheng-Lin Tsai and Ren-Song Tsay, “A Reuse-Distance Based Approach for Early-Stage Multi-level Cache Design Optimization,” SASIMI 2018
20. Hsin-I Wu, Chi-Kang Chen, Da-Yi Guo, and Ren-Song Tsay, “A Highly Efficient Virtualization-Assisted Approach for Full-System Virtual Prototypes,” SASIMI 2018. Best Paper Award.
21. Hsin-I Wu, Chi-Kang Chen, Tsung-Ying Lu, and Ren-Song Tsay, “A Highly Efficient Full-System Virtual Prototype Based on Virtualization-Assisted Approach,” DATE 2018
22. Chi-Kang Chen, Hsin-I Wu, Chi-Ting Hsiao, Ren-Song Tsay, “A Data Effect Aware Microcomponent-Based Estimation Approach for Accurate System-Level Memory Device Power Evaluation,” SASIMI 2016, Outstanding Paper Award.
23. Hsuan-Man Chen, Chi-Kang Chen, Hsin-I Wu, Ren-Song Tsay, “An Accurate Crowdsourcing-based Adaptive Fall Detection Approach Using Smart Devices,” ICHI 2016
24. Chi-Kang Chen, Hsin-I Wu, Chi-Ting Hsiao, and Ren-Song Tsay, “An Accurate and Flexible Early Memory System Power Evaluation Approach Using a Microcomponent Method,” CODES+ISSS 2016
25. Chi-Kang Chen, Zih-Ci Huang, Ren-Song Tsay, “An Accurate Processor Power Estimation Approach based on Microcomponent Structure Analysis,” SASIMI 2015
26. Hsin-I Wu, Li-chun Chen, Ren-Song Tsay, “An Effective Timing-Coherent Transactor Generation Approach for Mixed-level System Simulations,” SASIMI 2015
27. Zih-Ci Huang, Chi-Kang Chen, Ren-Song Tsay, “AROMA: A Highly Accurate Microcomponent-based Approach for Embedded Processor Power Analysis,” ASPDAC 2015
28. Li-chun Chen, Hsin-I Wu, Ren-Song Tsay, “Automatic Timing-Coherent Transactor Generation for Mixed-level Simulations,” ASPDAC 2015
29. Shu-Yung Chen, Chien-Hao Chen and Ren-Song Tsay, “An Activity-Sensitive Contention Delay Model for Highly Efficient Deterministic Full-System Simulations”, DATE, 2014
30. Chien-Min Lee, Chi-Kang Chen and Ren-Song Tsay, “A Basic-block Power Annotation Approach for Fast and Accurate Embedded Software Power Estimation,” VLSI-SoC 2013, pp.121~126
31. Pei-Chia Patty Lin, Evason Du, Ren-Song Tsay, “A Fast and Accurate Instruction-Oriented Processor Simulation Approach,” VLSI-DAT 2013
32. Mao-Lin Li, Chen-Kang Lo, Li-Chun Chen, Jen-Chieh Yeh, Ren-Song Tsay, “A Cycle Count Accurate TLM Bus Modeling Approach,” VLSI-DAT 2013
33. Fan-Wei Yu, Bo-Han Zeng, Yu-Hung Huang, Hsin-I Wu, Che-Rung Lee, and Ren-Song Tsay, “A Critical-Section-Level Timing Synchronization Approach for Deterministic Multi-Core Instruction-Set Simulations,” DATE 2013
34. Bo-Han Zeng, Ren-Song Tsay, and Ting-Chi Wang, “An Efficient Hybrid Synchronization Technique for Scalable Multi-Core Instruction Set Simulations,” ASPDAC 2013
35. Fong-Yuan Chang, Ren-Song Tsay,  Wai-Kei Mak, and Sheng-Hsiung Chen, “A Separation and Minimum Wire Length Constrained Maze Routing Algorithm Under Nanometer Wiring Rules,“ ASPDAC 2013
36. Chen-Kang Lo, Mao-Lin Li, Jen-Chieh Yeh, Ren-Song Tsay, “Automatic TLM Model Generation for Cycle-Count-Accurate Bus Simulation,” the 2012 DAC Work-In-Progress Session
37. Yu-Hung Huang, Hsin-I Wu, Ren-Song Tsay, “A Non-Intrusive Timing Synchronization Interface for Hardware-Assisted HW/SW Co-Simulation,” DAC 2012
38. Mao-Lin Li, Chen-Kang Lo, Li-Chun Chen, Hong-Jie Huang, Jen-Chieh Yeh, Ren-Song Tsay, “A Formal Full Bus TLM Modeling for Fast and Accurate Contention Analysis,” The 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2012) Outstanding Paper Award
39. Meng-Huan Wu, Cheng-Yang Fu, Peng-Chih Wang, Ren-Song Tsay,”A High-Parallelism Distributed Scheduling Mechanism for Multi-Core Instruction-Set Simulation,” DAC 2011
40. Ren-Song Tsay, “From Academic Ideas to Practical Physical Design Tools,” International Symposium on Physical Design (ISPD), pp. 9~12, 2011.
41. Chen Kang Lo, and Ren-Song Tsay, “Cycle-Count-Accurate Processor Modeling for Fast and Accurate System-Level Simulation,” Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 341, 346, 2011
42. Cheng-Yang Fu, Meng-Huan Wu, and Ren-Song Tsay, “A Shared-Variable-Based Synchronization Approach to Efficient Cache Coherence Simulation for Multi-Core Systems,” Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 347~352, 2011
43. Peng-Chih Wang, Meng-Huan Wu, and Ren-Song Tsay, “DOM: A Data-dependency-Oriented Modeling Approach for Efficient Simulation of OS Preemptive Scheduling,” Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 335~340, 2011
44. Fong-Yuan Chang, Ren-Song Tsay, Wai-Kei Mak, Sheng-Hsiung Chen, “Cut-Demand Based Routing Resource Allocation and Consolidation for Routability Enhancement,” ASPDAC 2011
45. Meng-Huan Wu, Fan-Wei Yu, Cheng-Yang Fu, Peng-Chih Wang, Ren-Song Tsay, “A Novel Timing Synchronization Method for Fast and Accurate Multi-Core Instruction-Set Simulators,” The 16th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2010)
46. Meng-Huan Wu, Yi-Shan Lu, Wen-Chuan Lee, Chen-Yu Chuang, Ren-Song Tsay, “Automatic Generation for Efficient Software TLM at Multiple Abstraction Layers,” The 16th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2010)
47. Meng-Huan Wu, Wen-Chuan Lee, Chen-Yu Chuang, and Ren-Song Tsay, “Automatic Generation of Software TLM in Multiple Abstraction Layers for Efficient HW/SW Co-simulation,” Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1177~1184, 2010
48. Kai-Li Lin, Chen-Kang Lo, and Ren-Song Tsay, “ Source-Level Timing Annotation for Fast and Accurate TLM Computation Model Generation,” ASPDAC 2010, pp. 235~240
49. Fongyuan Chang, Ren-Song Tsay, and Wai Kei Mak, “How to Consider Shorts and Guarantee Yield Rate Improvement for Redundant Wire Insertion,” Proceedings of the 2009 International Conference on Computer-Aided Design, pp. 33~38, 2009
50. Meng-Huan Wu, Cheng-Yang Fu, Peng-Chih Wang, and Ren-Song Tsay, “An Effective Synchronization Approach for Fast and Accurate Multi-core Instruction-set Simulation,” Proceedings of the seventh ACM international conference on Embedded software, 197~204, 2009, Grenoble, France
51. Yi-Len Lo, Mao-Lin Li, and Ren-Song Tsay, ” Cycle Count Accurate Memory Modeling in System Level Design,” CODES+ISSS’09, Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis, October 11-16, 287~293, 2009, Grenoble, France
52. Chen Kang Lo, and Ren Song Tsay, “ Automatic Generation of Cycle Accurate and Cycle Count Accurate Transaction Level Bus Models from a Formal Model,” in Proceedings of ASPDAC, pp.558-563, 2009
53. Ching-Te Chiu, Tsun-Hsien Wang, Wei-Ming Ke, Chen-Yu Chuang, Jhih-Siao Huang, Wei-Su Wong, and Ren-Song Tsay, “A 100mhz Real-Time Tone Mapping Processor With Integrated Photographic and Gradient Compression in 0.13 Um Technolgy,” IEEE Workshop on Signal Processing Systems, 25~30, 2008.
54. Ching-Te Chiu, Tsun-Hsien Wang, Wei-Ming Ke, Chen-Yu Chuang, Jhih-Rong Chen, Rong Yang, and Ren-Song Tsay, “Design Optimization Of a Global/Local Tone Mapping Processor on Arm Soc Platform for Real-Time High Dynamic Range Video,”, 15th IEEE International Conference on Image Processing, pp. 1400~1403, 2008

55. Ren-Song Tsay, “An Entrepreneurship Emulation Platform,” International Conference on Microelectronic Systems Education, 63~64, 2007

Domestic Conference Papers:

1. Jui-Hung Kao and Ren-Song Tsay, "Enhancing Transparency and Trust in Accounting with Triple-Entry Transactions and Digital Signatures in a Blockchain-based AIS Approach,” The 17th International Conference on Innovation, Management and Knowledge Community (iCIMKC 2023)
2. Zheng-Xun Jiang and Ren-Song Tsay, “Improving Performance and Fairness in Blockchain through Double-Linked and Proof-of-Refundable-Tax,” 第二十一屆離島資訊技術與應用研討會(ITOAI 2023) [Outstanding Paper Award]
3. Yi-Hung Huang, Yi-Chun Yang, Ren-Song Tsay, “A Distributed Self-Sovereign Access Control Mechanism for IoT,” DLT 2023
4. Young Ya, Yi-Chun Yang, Ren-Song Tsay, “Transaction Management for Distributed Self-Sovereign IoT Access Control,” DLT 2023
5. Yi-Chun Yang, Ren-Song Tsay, “Ureka: A Decentralized Access Management Framework for IoT Systems,” DLT 2023
6. Wei-Hsin Chang and Ren-Song Tsay, ”Ultra Secure and Reliable Private Key Recovery by Separating Permission and Possession,” TANET 2022
7. Kuo-Cheng Chin, Ren-Song Tsay, Hsin-I Wu and Tzu-Hsuan Su, “A Systematic Region-Based Interleaving Reduction Approach for Concurrent Bug Testing,” 33 VLSI Design/CAD Symposium, Taiwan, August 2022
8. Chong-Yin Lu, Ren-Song Tsay, Wey-shin Chang, and Hsiang-Ting Peng, “Based on Logarithmic Computing to Design an Embedded CNN Processor,” 33 VLSI Design/CAD Symposium, Taiwan, August 2022
9. Wei En Tsai, Kuo Cheng Chin, Borhan Lee, Wei Chung Chen and Ren Song Tsay, “iWalkSafe - Wearable Navigation Assistance for the Visually Impaired Based on Miniaturized Edge AI,” 33 VLSI Design/CAD Symposium, Taiwan, August 2022
10. Hsin-I Wu, Fong-Yuan Chang, Ren-Song Tsay, Kuan-Fu Lu, “CORONA: A k-COnnected RObust Interconnection Network Generation Algorithm,” 32 VLSI Design/CAD Symposium, Taiwan, August 2021
11. Yin-Chun Ling, Hsu-Hsun Chin, Hsin-I Wu, Ren-Song Tsay, Jui-Hung Kao, “Designing A Compact Convolutional Neural Network Processor on Embedded FPGAs,” 32 VLSI Design/CAD Symposium, Taiwan, August 2021
12. Hsin-I Wu, Da-Yi Guo, Hsu-Hsun Chin, Ren-Song Tsay, Zheng-Xun Jiang, “A Title: A Pipeline-Based Scheduler for Optimizing Latency of Convolution Neural Network Inference over Heterogeneous Multicore Systems, “ 31st VLSI Design/CAD Symposium, Taiwan, August 2020
13. Hsin-I Wu, Da-Yi Guo, Ren-Song Tsay and Guan-Shiue Li, “A Virtualization-Assisted Full-System Simulation Approach for the Verification of System Inter-Component Interactions, “ 30th VLSI Design/CAD Symposium, Taiwan, August 2019
14. Chia-Chi Lee, Hsin-Yu Ho, Hsin-I Wu and Ren-Song Tsay, “An Effective Early Multi-core System Shared Cache Design Method Based on Reuse-distance Analysis,” 29th VLSI Design/CAD Symposium, Taiwan, August 2018
15. Yin-Chun Ling, Hsin-I Wu, Chi-Kang Chen, Da-Yi Guo and Ren-Song Tsay, “A Virtualization-Assisted Approach for Highly Efficient Full-System Virtual Prototypes,” 29th VLSI Design/CAD Symposium, Taiwan, August 2018
16. Tzu-Yun Huang , Chien-Hao Chen, Hsin-I Wu , Chi-Kang Chen , Ren-Song Tsay, “Analytical Process Scheduling Optimization Using Scaling Factor for Heterogeneous Multi-core Systems”, 28th VLSI Design/CAD Symposium, Taiwan, August 2017
17. Bo-Yu Huang, Hsin-I Wu, Chi-Kang Chen, Ren-Song Tsay, “VIRA: A Virtualization-Assisted Approach for Highly Efficient and Accurate Full-System Simulations”, 28th VLSI Design/CAD Symposium, Taiwan, August 2017.
18. Kuo-Cheng Chin, Hsuan-Man Chen, Chi-Kang Chen, Hsin-I Wu, Ren-Song Tsay, “A Highly Reliable Fall Detection Approach Using Smart Devices on Real User Self-Adaptive Crowdsourcing-Based Framework,” 27th VLSI Design/CAD Symposium, Taiwan, August 2016
19. Da-Yi Guo, Chi-Ting Hsiao, Chi-Kang Chen, Ren-Song Tsay, “A Microcomponent-based Approach for Accurate System-Level Memory Power Estimation,” 27th VLSI Design/CAD Symposium, Taiwan, August 2016
20. Hsuan-Man Chen, Chi-Kang Chen, Hsin-I Wu, Ren-Song Tsay, “A Highly Accurate Fall Detection Approach Based on Crowdsourcing of Smart Devices,” Symposium on Digital Life Technologies 2016
21. Wei-Hsin Chang, Zih-Ci Huang, Chi-Kang Chen, Ren-Song Tsay, “AROMA: A Microcomponent-based Methodology for Accurate Embedded Processor Power Analysis,” 26th VLSI Design/CAD Symposium, Taiwan, August 2015
22. Yun Chang, Jyun-Hao Chang, Hsin-I Wu, Hsien-Lun Pai, Ren-Song Tsay, Wai-Kei Mak “An Efficient Approach for Synchronization-Function-Level Parallel Multi-Core Instruction-Set Simulations,” 26th VLSI Design/CAD Symposium, Taiwan, August 2015
23. Yu-Kang Hu, Chen-Kang Lo, Mao-Lin Li, Li-Chun Chen, Yi-Shan Lu, Ren-Song Tsay, Hsu-Yao Huang, Jen-Chieh Yeh, “Automatic Generation of Fast and Accurate TLM Models for Out-of-Order Pipelined Bus”, 26th VLSI Design/CAD Symposium, Taiwan, August 2015
24. Hsiang-Yi Wu, Li-Chun Chen, Hsin-I Wu, Ren-Song Tsay, “An Automatic Timing-Coherent-Based Transactor Generation Approach for Mixed-level Simulations,” 26th VLSI Design/CAD Symposium, Taiwan, August 2015
25. Pei-Chia Patty Lin, Hsuan-Yi Lin, Evason Du, Ren-Song Tsay “An Instruction-Oriented Approach for Fast and Accurate Processor Simulation,” 25th VLSI Design/CAD Symposium, Taiwan, August 2014
26. Shu-Yung Chen, Chien-Hao Chen, Cheng-Lin Tsai, and Ren-Song Tsay, “An Efficient Deterministic Full-System Simulations with Activity-Sensitive Contention Delay Model,” 25th VLSI Design/CAD Symposium, Taiwan, August 2014
27. Chien-Min Lee, Shin-yu Ho, and Ren-Song Tsay,”Fast and Accurate Embedded Software Power Estimation With A Basic-block Power Annotation,” 25th VLSI Design/CAD Symposium, Taiwan, August 2014
28. Chen-Kang Lo, Kuan-Hsin Lee,  Mao-Lin Li, Ren-Song Tsay, Hsu-Yao Huang, Jen-ChiehYeh, “FSM Based Models for Fast and Accurate Out-of-Order Pipelined Bus Simulation,” 24th VLSI Design/CAD Symposium, Taiwan, August 2013
29. Fan-Wei Yu, Wen-Jui Lee, Bo-Han Zeng, Yu-Hung Huang, Hsin-I Wu, Ren-Song Tsay, “A Novel Timing Synchronization Approach for Deterministic Multi-Core Instruction-Set Simulations,” 24th VLSI Design/CAD Symposium, Taiwan, August 2013
30. Bo-Han Zeng, Chien-Hao Chen, Ren-Song Tsay, “An Efficient and Scalable Hybrid Synchronization Techniques for Multi-Core Instruction Set Simulations,” 24th VLSI Design/CAD Symposium, Taiwan, August 2013
31. Yu-Hung Huang, Ching-Yu Chen, Yi-Shan Lu, Hsin-I Wu, and Ren-Song Tsay, “A Non-Intrusive Timing Synchronization Interface for Hardware-Assisted HW/SW Co-Simulation,” 23rd VLSI Design/CAD Symposium, Taiwan, August 2012
32. Mao-Lin Li, Shu-Yung Chen, Chen-Kang Lo, Li-Chun Chen, Ren-Song Tsay, Hong-Jie Huang, and Jen-Chieh Yeh, “An FSM-based modeling approach for fast and accurate bus contention simulation,“ 23rd VLSI Design/CAD Symposium, Taiwan, August 20
33. Cheng-Yang Fu, Hsien-Lun Pai, Meng-Huan Wu, and Ren-Song Tsay, ”A Fast and Accurate Cache Coherence Simulation for Multi-Core Systems,” 22nd VLSI Design/CAD Symposium, Taiwan, August 2011, pp.49~52
34. Chen Kang Lo, Zih-Ci Huang, Li-Chun Chen, Meng-Huan Wu, and Ren-Song Tsay, ”An Efficient and Cycle-Count-Accurate Processor for System-Level Simulation,” 22nd VLSI Design/CAD Symposium, Taiwan, August 2011, pp. 53~56
35. Peng-Chih Wang, Meng-Huan Wu, and Ren-Song Tsay, “A Data-dependency-Oriented Modeling Approach for Fast and Accurate Simulation of OS Preemptive Scheduling,” 22nd VLSI Design/CAD Symposium, Taiwan, August 2011, pp.57~60
36. Fong-Yuan Chang, Chi-Kang Chen, Ren-Song Tsay, Wai-Kei Mak, Sheng-Hsiung Chen,” Early-Stage Routability Improvement,” 22nd VLSI Design/CAD Symposium, Taiwan, August 2011, pp. 256~259
37. Meng-Huan Wu, Hsin-I Wu, Peng-Chih Wang, Cheng-Yang Fu, and Ren-Song Tsay, “Distributed Scheduling for Parallel Instruction-Set Simulation of Multi-Core Systems,” 22nd VLSI Design/CAD Symposium, Taiwan, August 2011, pp. 585~588
38. Meng-Huan Wu, Yu-Hung Huang, Cheng-Yang Fu, Peng-Chih Wang, and Ren-Song Tsay, “A Novel Synchronization Technique for Fast and Accurate Multi-core Instruction-set Simulation,” 21th VLSI Design/CAD Symposium, Kaohsiung, Taiwan, August 2010 (Best paper nomination, 選為國科會優良論文)
39. Kai-Li Lin, Pei-Jia Lin, Cheng-Kang Lo, and Ren-Song Tsay , “Fast and Accurate TLM Computation Model Generation Using Source-Level Timing Annotation,” 21st VLSI Design/CAD Symposium, Kaohsiung, Taiwan, August 2010 (選為國科會優良論文)
40. Yi-Len Lo, Li-Chun Chen, Mao-Lin Li, and Ren-Song Tsay, “A Cycle Count Accurate Timing Model for Fast Memory Simulation,” 21st VLSI Design/CAD Symposium, Kaohsiung, Taiwan, August 2010

ArXiv:

1. Chin, H. H., Tsay, R. S., & Wu, H. I. (2021). A High-Performance Adaptive Quantization Approach for Edge CNN Applications. arXiv preprint arXiv:2107.08382.

Patents:

  Taiwan –

1. 中華民國專利I507989, 黃子齊, 蔡仁松, 資源導向之嵌入式系統功率消耗分析方法METHOD OF RESOURCE-ORIENTED POWER ANALYSIS FOR EMBEDDED SYSTEM
2. 中華民國專利I507990, 吳孟寰, 蔡仁松, 「多核心指令集模擬之高平行化同步方法」A HIGH-PARALLELISM SYNCHRONIZATION APPROACH FOR MULTI-CORE INSTRUCTION-SET SIMULATION
3. 中華民國專利I378356, 吳孟寰, 傅正陽, 王鵬智, 蔡仁松, “多核心指令集之模擬方法與裝置,” METHOD AND DEVICE FOR MULTI-CORE INSTRUCTION-SET SIMULATION
4. 中華民國專利, 利茂霖, 羅振綱, 陳立君, 黃鴻杰, 葉人傑, 蔡仁松,「全匯流排之交易層級模擬方法以快速與精確的爭用分析/A Full Bus Transaction Level Modeling Approach for Fast and Accurate Contention Analysis」2011. (pending)
5. 中華民國專利, 王鵬智, 吳孟寰, 蔡仁松, 「資料相依導向模型以有效率模擬作業系統先佔式排程之方法」, 2011. (pending)
6. 中華民國專利, 吳孟寰, 蔡仁松, 「用以產生軟體交易層級模型之方法、系統及電腦可讀媒體」, 2010. (pending)
7. 中華民國專利, 李建旻, 羅振綱, 吳孟寰, 蔡仁松, 「模擬處理器功率消耗之系統及其方法」, 2010. (pending)

United States –

1. US Patent 9195788, Tzu-Chi Huang, Ren-Song, “Resource-oriented method of power analysis for embedded system.” U.S. Patent Application No. 14/016,305
2. US Patent 8875081, Fong-Yuan Chang, Sheng-Hsiung Chen, Tung-Chieh Chen, Ren-Song Tsay, Wai-Kei Mak, “Systems and methods for designing and making integrated circuits with consideration of wiring demand ration.” U.S. Patent Application No. 14/486,723.
3. US Patent 8549468 20110197174, Meng-Huan Wu and Ren-Song Tsay, “Method, System, and Computer Readable Medium for Generating Software Transaction-Level Modeling (TLM) Model,” U.S. Patent Application No. 12/701,810
4. US Patent 8423343, Meng-Huan Wu and Ren-Song Tsay, “A High-Parallelism Synchronization Approach for Multi-Core Instruction-Set Simulation,” 2013.3.7
5. US Patent 8,407,647, Fong-Yuan Chang, Sheng-Hsiung Chen, Tung-Chieh Chen, Ren-Song Tsay, Wai-Kei Mak, “Systems and methods for designing and making integrated circuits with consideration of wiring demand ration.”
6. US Patent 8352924, Meng-Huan Wu, Wen-Chuan Lee, Chen-Yu Chuang, and Ren-Song Tsay, “Method and Device for Multi-Core Instruction-Set Simulation,” 10/21/2010
7. US Patent 8336001, Fong-Yuan Chang, Wai-Kei Mak, and Ren-Song Tsay, ”Method For Improving Yield Rate Using Redundant Wire Insertion,” 05/05/2011
8. US Patent 5461576 “Electronic Design Automation Tool for the Design of a Semiconductor Integrated Circuit Chip,” Oct. 24, 1995 (58 citations)
9. US Patent 6009256 “Simulation/Emulation System and Method,” Dec. 28, 1999 (24 citations)
10. US Patent 6134516 “Simulation Server System and Method,” Oct. 17, 2000 (13 citations)
11. US Patent, Fong-Yuan Chang, Sheng-Hsiung Chen, Ren-Song Tsay, Wai-Kei Mak, “Separation and minimum wire length constrained maze routing method and system.” U.S. Patent Application No. 14/496,420.
12. US Patent 20120233410, Cheng-Yang Fu, Meng-Huan Wu, and Ren-Song Tsay, “Shared-Variable-Based (SVB) Synchronization Approach for Multi-Core Simulation,” 9/13/2012.
13. US Patent, Peng-Chih Wang, Meng-Huan Wu, and Ren-Song Tsay, “Data-dependency-Oriented Modeling Approach for Efficient Simulation of OS Preemptive Scheduling,” 2011. (pending)
14. US Patent, Chien-Min Lee, Chen-Kang Lo, Meng-Huan Wu, and Ren-Song Tsay, “System for Simulating Processor Power Consumption and Method of the Same,” 2010. (pending)
15. US Patent 20100269103, Trent Lo, and Ren-Song Tsay, “Method, System and Computer Readable Medium for Generating Software Transaction-Level Modeling (TLM) Model,” 10/21/2010.

Publications before 2005:

1. Tsay, Ren-Song, “Exact Zero Skew”, in The Best of ICCAD – 20 Years of Excellence in Computer-Aided Design, Kluwer Academic Publishers, 2003.
2. Tsay, Ren-Song, “TUTORIAL: Interconnect-Driven Performance Optimization for Deep Submicron Layout Systems” DAC, 1997.
3. Kenneth D. Boese, Andrew B. Kahng, Ren-Song Tsay, “Scan Chain Optimization: Heuristic and Optimal Solutions”, Research Report UCLA (1994) (7 citations)
4. Ho, J.-M., M. T. Ko and Ren-Song Tsay, “Assignment of Clock Driver”, Schloss Dagstuhl Seminar on Combinatorial Methods for VLSI/CAD, Oct. 1993 Germany.
5. Chang, C.-C., J. Lee, M. Stabenfeldt and Ren-Song Tsay, “A Practical All-Path Timing-Driven Place and Route Design System”, Proc. Asia-Pacific Conf. on Circuits and Systems, 1994, pp. 560-563. (8 citations)
6. Tsay, Ren-Song. An exact zero-skew clock routing algorithm. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 12(2):2.42-249, 1993. (Best Paper Award) (274 citations)
7. Shih, M., E.S. Kuh, and Ren-Song Tsay, “Timing-Driven System Partitioning by Constraints Decoupling Method,” Proc. 1993 IEEE Multichip Module Conf., pp. 164-169, March 1993. (5 citations)
8. Shih, M., E.S. Kuh, and Ren-Song Tsay, “Integer Programming Techniques for Multiway System Partitioning Under Timing and Capacity Constraints,” Proc. EDAC-Euroasic Conf., February 1993. (4 citations)
9. Tsay, Ren-Song and I. Lin, “Robin Hood: A System Timing Verifier for Multi-Phase Level-Sensitive Clock Designs,” Proceedings of IEEE International Conference on ASICs, pp. 516-519, September 1992.
10. Ho, J.-M. and Ren-Song Tsay, “Clock Tree Regeneration, ” Prof. IEEE GLS-VLSI’92, Feb. 1992.
11. Tsay, Ren-Song and S. C. Chang, “Early Wirability Checking and 2-D Congestion-Driven Circuit Placement.” In International Conference on ASIC, pp. 50–53, 1992. (14 citations)
12. Shih, M., E.S. Kuh, and Ren-Song Tsay, “Performance-Driven Partitioning on Multi-Chip Modules,” Proc. Design Automation Conference, pp. 53-56, June 1992. (37 citations)
13. Shih, M., E.S. Kuh, and Ren-Song Tsay, “System Partitioning for Multi-Chip Modules Under Timing and Capacity Constraints,” Proc. IEEE Multi-Chip Module Conference, pp. 123-126, March 1992. (2 citations)
14. Vijayan, G. and Ren-Song Tsay. “A new method for floorplanning using topological constraint reduction,” IEEE. Trans. on CAD, 10(12):1494-1501, December 1991. (28 citations)
15. Tsay, Ren-Song and J Koehl, “An analytic net weighting approach for performance optimization in circuit placement”, In Proc. ACM/IEEE Design Automation Conf., 1991, pp. 620-625. (53 citations)
16. Tsay, Ren-Song, “Exact Zero Skew”, Proc. of International Conference on Computer Aided Design, pp. 336–339(1991). (159 citations)
17. Tsay, Ren-Song and Ichiang Lin, “A system timing verifier for multiple-phase level-sensitive clock design,” Research Report RC 17272, IBM Yorktown, 1991.
18. Shih, M., E.S. Kuh, and Ren-Song Tsay, “Performance-Driven System Partitioning on Multi-Chip Modules,” IBM Research Division Research Report RC 17315 (#76556), October 1991.
19. Tsay, Ren-Song and Ernest Kuh, “A Unified Approach to Partitioning and Placement,” IEEE Trans. on Circuits and Systems, Vol. CAS-38, No. 5, pp. 521-533, May 1991. (58 citations)
20. Tsay, Ren-Song, and E.S. Kuh, “A Unified Approach to Partitioning and Placement,” IBM Research Report RC-15482 (#68859), February 9, 1990.
21. Vijayan, G. and Ren-Song Tsay, “Floorplanning by Topological Constraint Reduction”, ICCAD 1990: 106-109. 1989. (28 citations)
22. Parng, T. and Ren-Song Tsay, “A New Approach to Sea-of-gates Global Routing,” Proc. IEEE International Conference on Computer-Aided Design, Nov. 1989, pp. 52-55. (18 citations)
23. Daijavad, S., E. Polak, and S. Tsay, “A Combined Deterministic And Random Optimization Algorithm For The Placement Of Macro-Cells,” in International Workshop on Placement and Routing, Research Triangle Park, North Carolina, 1988.
24. Tsay, Ren-Song, E.S. Kuh, and C-P. Hsu, “PROUD: A Sea-Of-Gates Placement Algorithm,” IEEE Design and Test of Computers, pp. 44-56, December 1988. (141 citations)
25. Tsay, Ren-Song, E.S. Kuh, and C-P. Hsu, “Module Placement for Large Chips Based on Sparse Linear Equations,” International Journal of Circuit Theory and Applications, vol. 16, pp. 411-423, October 1988. (19 citations)
26. Tsay, Ren-Song, E.S. Kuh, and C-P. Hsu, “PROUD: A Fast Sea-of-Gates Placement Algorithm,” Proceedings of 25th Design Automation Conference, pp. 318-323, June 1988. (135 citations)
27. Daijavad, S., E Polak, and Ren-Song Tsay,” A combined deterministic and random optimization algorithm for the placement of macro-cells”, Technical Report No. UCB/ERL M87/86, 1987.
28. Tsay, Ren-Song, E.S. Kuh, and C-P. Hsu, “PROUD: A Fast Sea-of-Gates Placement Algorithm,” UCB/ERL Memorandum M87/79, November 1987.
29. Tsay, Ren-Song and E.S. Kuh, “A Unified Approach to Circuit Partitioning and Placement,” Proc. Princeton Conference on Information Sciences & Systems, pp. 155-160, March 1986. (6 citations)